UMS White Paper for testing purpose only

be implemented on a single die. With 75 processors, you have performance comparable to 13 or

more Pentium class processors on a chip, in a smaller die size and at much lower power.

The high performance of the UMS is achievable in real applications because the UMS architecture

fits the problems to be solved. Almost all applications that demand high performance have a useful

characteristic. They process large quantities of identical blocks of data, in the same way,

independently. The need for high performance comes from the large number of data blocks to be

processed in a unit of time, rather than from the complexity of the algorithms used to process them.

The blocks of data may be groups of pixels on a screen in image processing such as MPEG and

graphics processing, strips of print pixels in scanner and printer image processing and packets of

data in the case of network communications. In each case, the same algorithms are used to process

each data block essentially independent of other data blocks being processed.

Since the data blocks are processed independently, they can be processed in parallel. This is called

data parallelism. All blocks are processed using the same algorithms, and these algorithms can be

expressed in a software program. The resulting model is called Single Program Multiple Data,

(SPMD) model. In the SPMD model, performance is proportional to the number of processors

processing the blocks of data. Because of its large number of processors, the UMS achieves high

performance in SPMD applications.

Simple Programming Model

The SPMD model is a simple programming model, particularly compared to other models such as

SIMD and VLIW. In the SPMD model, you write a single program that runs on many processors.

Data blocks are processed independently, so you do not have to consider program interactions and

scheduling nor inter-program communication, to a first approximation. You write a single program

to process a single block of data, and you use this program for as many processors as you like to

process the data as fast as you like.

Coordinating the processors in not difficult, either. Each data block is a task to be processed, and

the tasks are, by definition, independent and interchangeable. When a processor finishes one block,

it goes to a task list and gets another. Performance is proportional to the number of processors

executing tasks. Unlike other models such as SIMD and VLIW, parallel operation is natural, and

no parallelizing compiler is required.

The simple, write-one-program model is also compatible with current high performance SPMD

applications. In these SPMD applications, the need for performance comes from the large number

of data blocks to be processed per unit time, not from the complexity of the program to process

each block. A small, simple program can achieve very high performance simply by running on

many processors at once.

White Paper 5.0 11/10/99 Page: 4  November 1999

Document Number 1001-0002

UMS White Paper

Complete Programmability

The UMS is a completely programmable system, including the I/O. All functions implemented in

hardware in an ASIC are implemented in software in the UMS. Programmable I/O is the “missing

link” in previous attempts to solve the ASIC design problem. Each system design requires its own

mix of I/O interfaces, many of them requiring high performance, and typically half of them are

custom interfaces to existing devices. If you have programmable computation but do not have

programmable I/O you have solved only half your problem. You still have to do significant

hardware design.