| UMS designs are scalable, both in hardware and software. Scalable in hardware means that the |
| performance of the UMS is proportional to the number of processors. Scalable in software means |
| that you use the same software for all UMS designs, independent of the number of processors used. |
| The scalable designs the UMS enables have powerful advantages. With a scalable design, one |
| design can serve multiple markets. You can have a low price and performance product with few |
| processors, a high price and performance product with many processors and a medium price, |
| medium performance product with a medium number of processors, all from a single design and all |
| running the same software. This multiplies design productivity, gives you a whole product line with |
| a single design and reduces time to market for a whole product line. |
| Scalable Designs for Technology Independence |
| The UMS enables scalable designs in software, essentially independent of the UMS hardware |
| running the software. This application software is independent of the number of processors in a |
| given technology. It is also independent of the number of processors in a new generation of silicon |
| technology. You run the same software on the new technology as on the old. All of the silicon |
| technology migration effort is confined to the single UMS hardware platform design effort of |
| implementing the UMS and its processors in the new technology. |
| Scalable UMS designs allow you to have multiple price point products from a single design. It also |
| allows you to easily move to the next generation of silicon. If the next generation of silicon |
| provides a 20% shrink in size, it also allows 25% more processors for the same size. With the new |
| process, you can have the same product price points based on silicon costs, and each product will |
| have 25% improved performance over the previous model. Not only can you reuse the software on |
| the new silicon; you can often reuse the market and pricing models for your products. |
| White Paper 5.0 11/10/99 Page: 7 November 1999 |
| Document Number 1001-0002 |
| UMS White Paper |
| Cradle UMS Technology |
| Cradle Technologies supplies UMS silicon products with software tools and libraries to support |
| them. Cradle plans to offer UMS standard silicon products that cover low cost, medium cost and |
| performance and high performance applications. Cradle offers software design tools for the UMS |
| that support software generation and simulation for the full chip. The software tools support both |
| software simulation and debug of UMS hardware. In addition to tools, Cradle will offer application |
| software libraries for a variety of applications. These libraries will include modules for popular I/O |
| devices. |
| Hardware Architecture |
| The UMS, as shown in Figure 2, is a multiprocessor system on a chip with programmable I/O for |
| interface to external devices. The UMS is a single chip consisting of clusters of processors |
| connected by a high bandwidth bus. These processor clusters, called Quads, communicate with |
| external DRAM and I/O interfaces through a DRAM controller and through a fully programmable |
| I/O system, respectively. Each Quad consists of four processor groups: hence the name Quad. |
| Each processor group is called a Multi-Stream Processor, or MSP. |
| The UMS uses a single 32-bit (expandable to 40+ bits) address for all register and memory |
| elements. Each register and memory element in the UMS has a unique address and is uniquely |
| addressable. |
| Quads |
| The quad is a cluster of processors. It is the primary unit of replication of the UMS. A UMS chip |
| has one or more Quads. Figure 3 shows a block diagram of a Quad. |
| Figure 3: Quad Block Diagram |
| MSP |
| PROGRAM |
| INTERFACE |
| PE |
| PE |
| PE |
| PE |
| MEM/ |
| GLOBAL BUS |
| CACHE |
| UTIL |
| DATA |
| PROG |
| DSE |
| DSE |
| DSE |
| DSE |
| DSE |
| DSE |
| DSE |
| DSE |
| MEM/ |
| DMA |
| CACHE |
| MEM |
| MEM |
| MEM |
| MEM |
| MEM |
| MEM |
| MEM |
| MEM |
| ECC |
| The Quad consists of four sets of processors, called Multi-Stream Processors (MSPs), program |
| and data memories, a programmable DMA unit and a global bus interface. |
| The MSP is the unit of processing for applications. An application uses one or more MSPs |
| depending on the performance required. Each MSP consists of a Processing Element (PE) and two |
| Digital Signal Engines (DSEs). The PEs are general purpose 32-bit processors, while the DSEs are |
| high performance computation engines. The DSEs do the work, and the PEs keep them busy. |
| White Paper 5.0 11/10/99 Page: 8 November 1999 |
| Document Number 1001-0002 |
