UMS White Paper for testing purpose only

Friday, 27 April 2012

be implemented on a single die. With 75 processors, you have performance comparable to 13 or

more Pentium class processors on a chip, in a smaller die size and at much lower power.

The high performance of the UMS is achievable in real applications because the UMS architecture

fits the problems to be solved. Almost all applications that demand high performance have a useful

characteristic. They process large quantities of identical blocks of data, in the same way,

independently. The need for high performance comes from the large number of data blocks to be

processed in a unit of time, rather than from the complexity of the algorithms used to process them.

The blocks of data may be groups of pixels on a screen in image processing such as MPEG and

graphics processing, strips of print pixels in scanner and printer image processing and packets of

data in the case of network communications. In each case, the same algorithms are used to process

each data block essentially independent of other data blocks being processed.

Since the data blocks are processed independently, they can be processed in parallel. This is called

data parallelism. All blocks are processed using the same algorithms, and these algorithms can be

expressed in a software program. The resulting model is called Single Program Multiple Data,

(SPMD) model. In the SPMD model, performance is proportional to the number of processors

processing the blocks of data. Because of its large number of processors, the UMS achieves high

performance in SPMD applications.

Simple Programming Model

The SPMD model is a simple programming model, particularly compared to other models such as

SIMD and VLIW. In the SPMD model, you write a single program that runs on many processors.

Data blocks are processed independently, so you do not have to consider program interactions and

scheduling nor inter-program communication, to a first approximation. You write a single program

to process a single block of data, and you use this program for as many processors as you like to

process the data as fast as you like.

Coordinating the processors in not difficult, either. Each data block is a task to be processed, and

the tasks are, by definition, independent and interchangeable. When a processor finishes one block,

it goes to a task list and gets another. Performance is proportional to the number of processors

executing tasks. Unlike other models such as SIMD and VLIW, parallel operation is natural, and

no parallelizing compiler is required.

The simple, write-one-program model is also compatible with current high performance SPMD

applications. In these SPMD applications, the need for performance comes from the large number

of data blocks to be processed per unit time, not from the complexity of the program to process

each block. A small, simple program can achieve very high performance simply by running on

many processors at once.

White Paper 5.0 11/10/99 Page: 4  November 1999

Document Number 1001-0002

UMS White Paper

Complete Programmability

The UMS is a completely programmable system, including the I/O. All functions implemented in

hardware in an ASIC are implemented in software in the UMS. Programmable I/O is the “missing

link” in previous attempts to solve the ASIC design problem. Each system design requires its own

mix of I/O interfaces, many of them requiring high performance, and typically half of them are

custom interfaces to existing devices. If you have programmable computation but do not have

programmable I/O you have solved only half your problem. You still have to do significant

hardware design.

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The Universal Micro System Hardware Performance with Software Convenience

Abstract

The demands of digital image processing, communications and multimedia applications are

growing more rapidly than traditional design methods can fulfil them. Previously, only custom

hardware designs could provide the performance required to meet the demands of these

applications. However, hardware design has reached a crisis point. Hardware design can no longer

deliver a product with the required performance and cost in a reasonable time for a reasonable risk.

Software based designs running on conventional processors can deliver working designs in a

reasonable time and with low risk but cannot meet the performance requirements. Cradle

Technologies offers the Universal Micro System (UMS) as a solution to these problems The UMS

is a completely programmable (including I/O) system on a chip that combines hardware

performance with the fast time to market, low cost and low risk of software designs.

Today’s Challenge

Digital image processing, communications and multimedia applications are growing at an

explosive rate and are creating ever-increasing demands for computation and data management in

the systems that implement them. The performance demands of these applications are too high to

be met by conventional RISC or DSP processors. They have traditionally been met by custom

designed silicon in the form of Application Specific Integrated Circuits (ASICs) and Application

Specific Standard Products (ASSPs).

Customers and vendors design ASICs and ASSPs to provide the necessary system performance for

the current generation of silicon processes. Each new generation of silicon (e.g. going to 0.25

micron from 0.35 micron) requires a new round of ASIC and ASSP design. New designs are

required because each new generation of silicon has the potential of increased performance and

functionality for the same cost when compared to the previous generation.

Unfortunately, the ASIC and ASSP approach to high performance system design has been unable

to keep up with the continual demands of process improvement. Each round of process

improvement provides the capability of more transistors in a new product for the same cost as the

previous product. With more transistors, the new product requires more design time and effort than

the previous product. Improving design tools can help to reduce the effort. However even with

improvements in tools, there is a problem. Process capability in transistors per unit area has been

improving at over 50% per year, while design capability in transistors per designer per year has

been improving at less than 30% per year. If the designer population does not grow rapidly and

continually (and it has not), fewer designs per year can be implemented resulting in unmet demand.

Potentially successful products are not created because there is not enough talent available to make

them.

Copyright © 1999 Cradle Technologies, Inc. All rights Reserved. UMS and Multi Stream Processor are trademarks of Cradle

Technologies, Inc. All other trademarks or brand names mentioned herein are trademarks or registered trademarks of their respective

holders. Printed in the U.S.A

UMS White Paper

Bigger designs bring other problems. It takes more designers to create the design, the design takes

significantly longer to create and debug, and you have increased the risk of missing the market

window. A related problem is that product cycles are getting shorter. With the design taking longer

and product cycles getting shorter, the market can change and invalidate your product before you

finish the design.

The problem with ASIC and ASSP design is that it is hardware design. Hardware design is

relatively difficult, time consuming, inflexible and specialized relative to software design.

Hardware designs are also not very reusable when compared to software designs. Significant

design effort is often required to transfer a hardware design from the current process generation to

a new generation.

What is needed is a system approach that combines the high performance associated with hardware

with the short design time, flexibility and reusability of software. A new architecture called the

Universal Micro System (UMS) fills this need and fills it in a way that provides major advantages

over all other approaches that have been tried. The UMS provides the performance of hardware

designs with the rapid design time of software designs. Figure 1 shows the UMS relative to other

approaches in terms of system performance and design performance measured in designs per year.

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